The present invention relates to a signal transmission bus system for transmitting an electrical signal, such as a high-speed digital signal with a frequency of several gigahertz or more, over a transmission line from a driver circuit to a receiver circuit.
A conventional signal transmission bus system, depicted in FIG. 21, includes a transmission line 101, a driver circuit 102, and a receiver circuit 103 formed in or mounted on a circuit substrate 104. In a typical application, the driver circuit 102 and receiver circuit 103 are disposed in separate integrated-circuit (IC) chips, which are mounted on the circuit substrate 104. A power-supply pattern 105 and a ground pattern 106 are formed within the circuit substrate 104. The power-supply pattern 105 supplies power from a power supply, generically denoted Vdd, to the driver circuit 102, receiver circuit 103, and other circuits. Although shown as a line in the drawing, the power-supply pattern 105 may occupy part or all of a plane in the circuit substrate 104. A ground pattern 106, likewise having a broad planar extent, connects the driver circuit 102, receiver circuit 103, and other circuits to the ground side of the power supply, denoted by the conventional ground symbol and the letters GND. The transmission line 101 is configured as a microstrip transmission line.
The driver circuit 102 and receiver circuit 103 are complementary metal-oxide-semiconductor (CMOS) circuits, each having a p-channel metal-oxide-semiconductor field-effect transistor (hereinafter, pMOS transistor) with its source electrode coupled to the power-supply pattern 105, an n-channel metal-oxide-semiconductor field-effect transistor (hereinafter, nMOS transistor) with its source electrode coupled to the ground pattern 106, an input terminal connected to the gate electrodes of these two transistors, and an output terminal connected to the drain electrodes of the two transistors. The two ends of the transmission line 101 are coupled to the output terminal of the driver circuit 102 and the input terminal of the receiver circuit 103. The input impedance of the receiver circuit 103 exceeds the characteristic impedance of the transmission line 101.
The driver circuit 102 receives a transmit input signal TS from an external source, and places a corresponding transmitted signal on the transmission line 101. The receiver circuit 103 receives the transmitted signal and generates a corresponding receive output signal RS.
One advantage of a CMOS driver circuit such as the driver circuit 102 is its low power dissipation. Power dissipation is low because significant current flows only when the transmit input signal TS changes state.
A high-to-low transition of the transmit input signal TS causes current (denoted ILH) to flow from the power-supply pattern 105 through the pMOS transistor in the driver circuit 102 into the microstrip transmission line 101. On the microstrip transmission line 101, the transmitted signal propagates as an electromagnetic wave from the driver circuit 102 to the receiver circuit 103, changing the potential level sensed by the receiver circuit 103 from low to high. In the power-supply pattern 105, a flow of charge occurs as electrons drift from the driver circuit 102 toward the power supply Vdd. Repeated at each high-to-low transition of the transmit input signal TS, this flow of charge creates a current flow with an alternating (ac) component in the power-supply pattern 105.
Similarly, a low-to-high transition of the transmit input signal TS causes current (denoted IHL) to flow from the microstrip transmission line 101 through the nMOS transistor in the driver circuit 102 into the ground pattern 106. On the microstrip transmission line 101, the transmitted signal again propagates as an electromagnetic wave from the driver circuit 102 to the receiver circuit 103, changing the potential level sensed by the receiver circuit 103 from high to low. In the ground pattern 106, a flow of charge occurs as electrons drift from ground toward the driver circuit 102. Repeated at each low-to-high transition of the transmit input signal TS, this flow of charge creates a current flow with an ac component in the ground pattern 106.
If, for example, the power-supply voltage Vdd is 3.3 volts, the transistors in the driver circuit 102 have on-resistances of fifteen ohms (15 xcexa9) and off-resistances of one hundred thousand ohms (100 kxcexa9), and the resistance of the transmission line 101 is one hundred ohms (100 xcexa9), then the so-called dark current that flows from the power supply through the power-supply pattern 105 to the transmission line 101 when the transmission line 101 is at the low (ground) potential level, and from the transmission line 101 through the ground pattern 106 to ground when the transmission line 101 is at the high (Vdd) potential level, has the comparatively small value of three hundred thirty microamperes.
3.3 V/(100 xcexa9+100 kxcexa9)=330 xcexcA
If the signal propagation time on the transmission line 101 is one nanosecond (1 ns), then during that one nanosecond, the current ILH or IHL flowing into or out of the microstrip transmission line 101, charging or discharging the capacitance of the transmission line 101, has the comparatively large value of twenty-nine milliamperes.
xe2x80x833.3 V/(15 xcexa9+100 xcexa9)=29 mA
If the transmit input signal TS is a high-speed digital signal with a frequency of several gigahertz (GHz), for example, then an alternating current component of comparable frequency, with a magnitude equal to the difference between the above two current values, is generated in the power-supply pattern 105 and ground pattern 106. This comparatively large, high-frequency ac component can perturb the power-supply and ground potentials and affect the signal transmission bus system as a whole. Resonating with stray inductances and capacitances, it can cause the signal transmission bus system to malfunction.
Another problem is waveform distortion due to substantially total reflection of the transmitted signal at the receiver circuit 103. If, for example, TS transitions occur at frequencies of several gigahertz and the signal propagation time on the transmission line 101 is one nanosecond, then each reflection may distort multiple pulse waveforms, which are propagating simultaneously in the transmission line 101, and each waveform may be distorted by multiple reflections. The reflection distortions are further increased if the transmission line 101 is connected as a signal bus to multiple receiver circuits.
The above resonance effects and multiple reflection effects also generate electromagnetic radiation, which can give rise to eddy currents in extended planar areas of the power-supply pattern 105 and ground pattern 106. The eddy currents in turn generate further electromagnetic radiation, which becomes electromagnetic interference (EMI) affecting other circuits on the circuit substrate 104.
Another problem is that when the TS frequency is high enough to make the TS pulse width less than the signal propagation time (e.g., 1 ns) on the transmission line 101, a large current (either ILH or IHL) flows almost continuously, so the CMOS advantage of low power dissipation is lost.
As a solution to the problems of the signal transmission bus system shown in FIG. 21, the present inventors have proposed the signal transmission bus system shown in FIG. 22 (disclosed in Japanese Unexamined Patent Publication No. 10-348270). The transmission line in this system is a transmission line pair 201 comprising parallel signal transmission lines 201a, 201b of equal length, interconnected by a termination resistance 202 at one end, connected to a driver circuit 203 at the other end, and having one or more branching sections 204 (two are shown) at intermediate points between the two ends. The branching sections 204 couple the transmission line pair 201 to respective receiver circuits 205. The system also includes a power-ground line pair 206, comprising a power-supply line 206a and a parallel ground line 206b of equal length. The above components are disposed on a circuit substrate 207, the driver circuit 203 being part of an IC chip 211, the receiver circuits 205 being disposed in other IC chips 212.
The termination resistance 202 is matched to the characteristic impedance of the transmission line pair 201.
The driver circuit 203 is a driver of the current-switch type, the current switch being formed by a pMOS transistor Q1 and an nMOS transistor Q2 coupled in series between the power-supply line 206a and ground line 206b, in parallel with an nMOS transistor Q3 and a pMOS transistor Q4 also coupled in series between the power-supply line 206a and ground line 206b. The connections to the power-supply line 206a and ground line 206b pass through respective series resistances 208, 209. The transmit input signal TS is applied to the gate electrodes of all four transistors Q1, Q2, Q3, Q4. The node at which transistors Q1 and Q2 are interconnected is coupled to transmission line 201a, while the node at which transistors Q3 and Q4 are interconnected is coupled to transmission line 201b. Incidentally, bipolar transistors may be used instead of MOS transistors in the current switch.
The driver circuit 203 supplies a transmitted signal to the transmission line pair 201, responsive to the transmit input signal TS. The transmitted signal is a complementary signal having mutually complementary components that propagate on transmission lines 201a and 201b, respectively. The driver circuit 203 interchanges these complementary components, thereby inverting the polarity of the complementary signal, each time the TS level changes (from high to low, or from low to high).
Each branching section 204 diverts a small part of the energy of the complementary signal on the transmission line pair 201 to the coupled receiver circuit 205, which senses the signal without significantly disturbing its propagation on the transmission line pair 201. The receiver circuit 205 is, for example, a differential amplifier.
A driver circuit of the current-switch type enables current to flow steadily from the power supply Vdd to ground, regardless of whether the transmit input signal TS is high or low. This direct current (dc) flow is necessary if digital signals are to be transmitted at frequencies above five hundred megahertz (500 MHz). At frequencies that high, a CMOS driver of the type shown in FIG. 21 cannot supply charge to the transmission line fast enough to keep up with the transmit input signal; switching the currents ILH and IHL on and off at that high a frequency requires too much energy. The driver circuit 203 in FIG. 22, however, only has to change the direction of charge movement on the transmission line pair 201, which it can do at high speed while maintaining a steady dc flow from the power supply (Vdd) to ground.
By using a transmission line pair 201 comprising two parallel signal transmission lines 201a, 201b of equal length, the signal transmission bus system shown in FIG. 22 can transmit digital signals at rates up to several gigahertz. Sinewave signals can be transmitted at frequencies more than five times higher than the maximum digital signal rate. No reflection occurs at the end of the transmission line pair 201, because the termination resistance 202 matches the characteristic impedance of the signal transmission lines 201a and 201b. A signal transmission bus system of this type thus combines a simple structure with ideal signal-transmission properties.
This signal transmission bus system is not entirely free of problems, however. Since the transistors Q1, Q2, Q3, Q4 switch on and off simultaneously, they pass simultaneously through a partly-on state, halfway between the on and off states, in which current flows directly from the power-supply line 206a to the ground line 206b through transistors Q1 and Q2, and through transistors Q3 and Q4, bypassing the transmission line pair 201. At each transition of the transmit input signal TS, there is thus a brief instant during which the power-supply line 206a is semi-short-circuited to the ground line 206b. This causes common-mode noise, in which the ground potential rises momentarily and the power-supply potential (Vdd) falls momentarily. A small amount of differential-mode noise may also occur.
As an example, suppose that the power-supply voltage Vdd is 3.3 V, the characteristic impedance of each signal transmission line 201a, 201b is 100 xcexa9, the termination resistance is 100 xcexa9, and the resistance value of each series resistance 208, 209 is also 100 xcexa9. Let it further be assumed that transistors Q1 to Q4 have identical switching characteristics, with an on-resistance of 15 xcexa9, an off-resistance of 100 kxcexa9, and a resistance of 500 xcexa9 in the state halfway between the on and off states.
When the transistors Q1 to Q4 in the current switch are not being switched, the total series resistance of transistors Q1 and Q2 and series resistances 208, 209 has the following value, which is also the total series resistance of transistors Q3 and Q4 and series resistances 208, 209.
(2xc3x97100 xcexa9)+(100 kxcexa9+15 xcexa9)=100215 xcexa9
The current conducted through transistors Q1 and Q2 has the following value, as does the current conducted through transistors Q3 and Q4.
3.3 V/100215 xcexa933 xcexcA
During non-switching times, the total current conducted directly through the current switch from the power-supply line 206a to the ground line 206b is only 66 xcexcA.
When switching occurs, at the instant halfway through the switching period, the total series resistance on the direct path through each pair of transistors has the following value.
(2xc3x97100 xcexa9)+(2xc3x97500 xcexa9)=1.2 kxcexa9
The short-circuit current conducted on each direct path at this instant thus has the following value.
3.3 V/1.2 kxcexa9=2.75 mA
The signal current conducted through the transmission line pair 201 at non-switching times has the following value.
3.3 V/(2xc3x97100 xcexa9+2xc3x9715 xcexa9+100 xcexa9)=10 mA
These two current values can be compared as follows.
2.75 mA/10 mA=27.5%
Halfway through the switching period, accordingly, the short-circuit current becomes too large to be ignored. Since there are two short-circuit paths in the driver circuit 203, if the two paths switch with exactly the same timing, the total instantaneous short-circuit current reaches twice the above value (55% of the normal signal current flow through the transmission line pair 201). If the timing is skewed, the short-circuit current changes in a complex pattern including high-frequency components, which also cause significant noise problems.
A similar short-circuit current flows through the driver circuit 102 in FIG. 21 at switching instants. The problems caused by this short-circuit current did not become noticeable, however, because this driver circuit 102 is not used with very high-frequency signals.
The common-mode noise due to the above short-circuit current occurs on a shorter time scale than even the rise time of the transmitted digital signal; the common-mode noise includes frequency components more than ten times higher than those of the transmitted digital signal. The common-mode noise leads to power and ground potential perturbations that affect the entire signal transmission bus system. Through resonance with stray inductances and capacitances, these perturbations of the signal transmission system as a whole produce electromagnetic radiation.
One way to reduce the occurrence of common-mode noise is to insert a bypass capacitor, also referred to as a decoupling capacitor, between the power-supply line and the ground line, near the driver circuit, to supply extra charge when sudden current changes occur. A bypass capacitor, however, has its own parasitic inductance, which functions as an impedance when charge is being supplied in response to sudden current changes, impeding the supply of charge and inducing voltage noise in the power supply and ground potentials.
FIG. 23 shows an evaluation system that the inventors have used to evaluate common-mode noise. The IC chip 211 including the driver circuit 203 was mounted on an evaluation board 221 together with a bypass capacitor 222, a resistor 223, and probe terminals 224, 225, 226.
The bypass capacitor 222 was a ceramic chip capacitor measuring one millimeter by one-half millimeter in size (size 1005, 1.0 mmxc3x970.5 mm), with a capacitance of one-tenth of a microfarad (0.1 xcexcF). It was mounted between the power-supply line 206a and ground line 206b at a point near the IC chip 211. The resistor 223 was connected to the output terminals D1 and D2 of the driver circuit 203, and had a resistance of 100 xcexa9. Probe terminal 224 was coupled to the ground line 206b, probe terminal 225 to output terminal D1 of the driver circuit 203, and probe terminal 226 to output terminal D2 of the driver circuit 203.
In the evaluation system in FIG. 23, the supply voltage Vdd was 3.3 V and the input signal VIN was a 100-MHz signal with an amplitude of 2.4 V. The probe terminals 224, 225, 226 were contacted by field-effect-transistor (FET) probes. Measurements were made of the voltage V(D1-D2) across the two output terminals, the voltage V(D1-GND) of output terminal D1 with respect to ground, and the voltage V(D2-GND) of output terminal D2 with respect to ground.
An example of the observed voltage waveforms is shown in FIGS. 24A, 24B, and 24C. FIG. 24A shows the differential voltage waveform V(D1-D2) across the driver output terminals D1 and D2. FIG. 24B shows the voltage waveforms V(D1-GND) and V(D2-GND) of each output terminal with respect to ground, and the sum V(D1-GND)+V(D2-GND) of these two voltages. FIG. 24C shows only the sum waveform V(D1-GND)+V(D2-GND).
As can be seen from FIGS. 24B and 24C, the parasitic inductance of the bypass capacitor 222 prevents it from instantly supplying the charge needed during the sudden current changes that occur when the driver circuit is switching, allowing considerable common-mode noise to appear on both of the outputs of the driver circuit; that is, on both V(D1-GND) and V(D2-GND). Both the frequency components and the intensity of the common-mode noise are high enough to cause significant EMI problems, even though the common-mode noise does not affect the transmitted signal itself. Since the driver circuit outputs a differential voltage signal, the common-mode noise cancels out, giving the transmitted signal the comparatively noise-free V(D1-D2) waveform shown in FIG. 24A.
The measurements described in FIG. 23 and FIGS. 24A to FIG. 24C indicate that an external bypass capacitor such as a ceramic chip capacitor is incapable of eliminating the common-mode noise that occurs during the switching of the driver circuit, because of the parasitic inductance of the bypass capacitor. This is true even if a low-inductance capacitor (LICA) is employed as the external bypass capacitor. The only type of capacitor that can eliminate the common-mode noise is an embedded capacitor disposed together with the driver circuit inside the IC chip. Embedding the capacitor in the chip reduces its parasitic inductance to a substantially negligible level, such as one-tenth of a nanohenry (0.1 nH).
The power-supply and ground perturbations caused by the parasitic inductance of the bypass capacitor will be described in further detail below, with reference to a simulation performed with the well-known Simulation Program with Integrated Circuit Emphasis (SPICE).
Equivalent circuit diagrams of the signal transmission bus system to which the SPICE simulator was applied are shown in FIGS. 25A to 25D. The bypass capacitor is capacitor C1, and its parasitic inductance is represented by inductance L1. Bipolar npn transistors Q1 and Q2 are equivalent to the pMOS transistors in a CMOS driver circuit (see the signal transmission bus system 104 in FIG. 21), while bipolar pnp transistors Q3 and Q4 are equivalent to the nMOS transistors of a CMOS driver circuit. Transmission lines T1 and T2 are equivalent to the signal transmission lines, while transmission line T3 is equivalent to the power line. The equivalent circuits in FIGS. 25A to 25d differ only in the capacitance and inductance values (C1 and L1) assigned to the bypass capacitor. This capacitance (C1) is one hundred nanofarads (100 nF) in FIGS. 25A and 25B, and ten nanofarads (10 nF) in FIGS. 25C and 25D. The inductance (L1) is one-tenth of a nanohenry (0.1 nH) in FIGS. 25A and 25C, and one nanohenry (1 nH) in FIGS. 25B and 25D. Capacitance values C2 to C5, inductance values L2 and L3, resistance values R1 to R7, and the characteristics of the power-supply voltages V1 and V2, transmission lines T1 to T3, and transistors Q1 to Q4 are the same in all four circuits.
The SPICE simulator was used to obtain waveforms at node N2 (the positive terminal of power supply V2) and node N3 (at which inductance L1 and transistor Q1 are interconnected) when a square wave was applied at node N1 (the positive terminal of power supply V1). The simulated waveforms obtained from the equivalent circuits in FIGS. 25A to 25D are shown in corresponding FIGS. 26A to 26D. V(N1), V(N2), and V(N3) indicate voltages at nodes N1, N2, and N3, respectively, while I(L1) indicates the voltage across inductance L1 due to the charging and discharging of capacitance C1, and I(R5) indicates the ac component of the voltage across resistance R5.
Conventional wisdom calls for the bypass capacitor to have a capacitance of 100 nF or more, but the simulated waveforms indicate that if the parasitic inductance of the bypass capacitor is 0.1 nH or less, a capacitance of only 10 nF, one-tenth the conventional value, provides an adequate decoupling effect.
Common-mode noise can also be eliminated from the current-switch driver circuit shown in FIG. 22 by use of a bypass capacitor with a parasitic inductance of 0.1 nH or less, but a parasitic inductance value that small cannot be achieved with an external bypass capacitor. The only choice is to embed the bypass capacitor inside the IC chip, as mentioned above, preferably close to the driver circuit. Further information is given in the patent publication cited above.
Thus with a driver circuit of the current-switch type described above, there is the problem that during signal transition periods (when the transistors in the driver circuit are switching), the impedances seen from the power supply and ground undergo momentary changes, due to the dynamic changes in the transistor impedances, and short-circuit current is permitted to flow, generating common-mode noise (and a small amount of differential-mode noise) that leads to power-supply and ground perturbations. To eliminate this common-mode noise, it is necessary to embed a bypass capacitor inside the IC chip, near the driver circuit, but that constrains the design of the IC chip.
An object of the present invention is to reduce power-supply and ground disturbances caused by transmission of high-speed signals.
Another object of the invention is to increase signal transmission speeds.
Another object is to simplify the decoupling of power-supply and ground lines.
The invented driver circuit receives power at different potentials from a first power supply and a second power supply, and receives an input signal having a first level and a second level. The driver circuit supplies a complementary signal to a signal transmission line pair, which has first and second signal transmission lines, by closing a first current path between the first power supply and the first signal transmission line, and a second current path between the second power supply and the second signal transmission line, when the input signal is at the first level. When the input signal is at the second level, the driver circuit opens the first current path and second current path, and closes a third current path between the first power supply and the second power supply, bypassing the signal transmission line pair, so that no complementary signal is supplied. The first and second signal transmission lines are mutually parallel and have equal length.
The second power supply may be a ground supply.
The driver circuit behaves as a dc circuit, conducting current from the first power supply to the second power supply via the first current path, the signal transmission line pair, and the second current path when the input signal is at the first level, and via the third current path when the input signal is at the second level. During transitions between the two input signal levels, the impedance of the first and second current paths increases while the impedance of the third current path decreases, or vice versa, so the impedance seen from the power supplies remains substantially constant. Consequently, the driver circuit generates comparatively little common-mode noise, does not significantly disturb the power-supply potentials, and can transmit signals at high speed without producing significant electromagnetic interference. These effects are furthermore obtained without reliance on the decoupling of the power-supply lines by a bypass capacitor; in particular, it is not necessary to embed a bypass capacitor in the driver circuit. Thus while a bypass capacitor may be used, there are no tight constraints on its mounting position, parasitic inductance, and other attributes.
The invented receiver circuit includes a differential amplifier having a pair of differential input terminals, and a termination transistor coupled between the differential input terminals. The differential input terminals are coupled through respective resistances to a signal transmission line pair of the type described above. The differential amplifier generates an output signal indicating whether or not a complementary signal is present on the signal transmission line pair.
When the complementary signal is present, it charges the input capacitance of the differential amplifier. When the complementary signal disappears, the stored charge is rapidly discharged through the termination transistor, enabling the signal-absent state to be sensed quickly.
The invented signal transmission bus system comprises the signal transmission line pair described above, and a termination resistance interconnecting the first signal transmission line and second signal transmission line at one end of the signal transmission line pair, matching the characteristic impedance of the first signal transmission line and second signal transmission line. The signal transmission line pair is coupled to at least one driver circuit of the invented type, or at least one receiver circuit of the invented type. Several connection configurations are possible.
In one configuration, a driver circuit is coupled to the end of the signal transmission line pair opposite the termination resistance, and at least one receiver circuit is coupled to the signal transmission line pair at a point intermediate between its two ends, through a branching section.
In another configuration, a receiver circuit is coupled to the end of the signal transmission line pair opposite the termination resistance, and at least one driver circuit is coupled to the signal transmission line pair at a point intermediate between its two ends, through a branching section.
In still another configuration, a first IC chip is coupled to the end of the signal transmission line pair opposite the termination resistance, and a second IC chip is coupled to the signal transmission line pair at a point intermediate between its two ends, through a branching section. Each of the two IC chips includes both a driver circuit and a receiver circuit, enabling complementary signals to be transmitted in both directions on the signal transmission line pair.
In the invented signal transmission bus system, the termination resistance prevents reflection at the end of the signal transmission line pair. Use of the invented driver circuit and/or the invented receiver circuit enables high-speed signal transmission.
When the invented driver circuit is used in the invented signal transmission bus system, the termination resistance may be configured as two resistances coupled in series, the node between the two resistances being coupled to the second power supply. This configuration stabilizes the potential of the signal transmission line pair when the complementary signal is absent, providing the signal transmission line pair with added immunity to external electromagnetic interference.
The invented driver circuit may also include a noise-elimination resistance, coupled between the first signal and second signal transmission lines, to absorb reflections that may occur at intermediate points on the signal transmission line pair. The noise-elimination resistance may be configured as two resistances coupled in series, the node between the two resistances being coupled to the second power supply, to stabilize the potential of the signal transmission line pair when the complementary signal is absent and provide added immunity to external electromagnetic interference.
Power from the first and second power supplies may be supplied to the driver circuit over a power line pair comprising parallel lines of equal length. The inductances of these parallel lines will then cancel out, so that the power line pair is substantially free of reactance. This arrangement helps to prevent electromagnetic disturbances on the power lines. A bypass capacitor may be coupled to the power line pair, to reduce the effects of electromagnetic noise generated by other circuits.
One or more resistances may be inserted in series between the driver circuit and the power supplies, to reduce current consumption and thus reduce power dissipation.
The receiver circuit, driver circuit, or IC chip coupled to the signal transmission line pair at an intermediate point thereon may be coupled through a branch transmission line pair comprising parallel lines of equal length. When a driver circuit is coupled in this way, the characteristic impedance of the branch transmission line pair is preferably one-half the characteristic impedance of the signal transmission line pair.
The signal transmission bus system may include two or more signal transmission line pairs, coupled to respective driver circuits or receiver circuits by branch transmission line pairs. A branch transmission line pair may then cross a signal transmission line pair to which it is not coupled. In one preferred structure in this case, the first and second signal transmission lines forming the signal transmission line pair are mutually separated by a first dielectric layer, the first and second branch transmission lines forming the branch transmission line pair are mutually separated by a second dielectric layer, and the signal transmission line pair is separated from the branch transmission line pair by a third dielectric layer at least twice as thick as the first and second dielectric layers. The inductances of the first and second signal transmission lines then cancel out, and the inductances of the first and second branch transmission lines cancel out, so that the signal transmission line pair and branch transmission line pair have zero reactance. The signal transmission line pair and branch transmission line pair are also sufficiently separated from each other that mutual interference between the signals on them is prevented at the crossover point.
If the receiver circuit has a sufficiently high input resistance and a sufficiently low input capacitance, it may be coupled directly to the signal transmission line pair.